Combining Several Paradigms for Circuit Validation and Verification
نویسندگان
چکیده
منابع مشابه
Combining Simulation and Formal Verification for Integrated Circuit Design Validation
The correct design of complex hardware continues to challenge engineers. Bugs in a design that are not uncovered in early design stage can be extremely expensive. Simulation is a predominantly used tool to validate a design in industry. Formal verification overcomes the weakness of exhaustive simulation by applying mathematical methodologies to validate a design. The work described here focuses...
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تاریخ انتشار 2004